[coyotos-dev] I love Intel

[Jonathan S. Shapiro]

Warning: rant ahead.

The Intel P5 processors have a horrible bug known as the F00F bug (after
the opcode sequence that generates it). Hand-coded user-mode code can
cause the entire machine to lock up. For those who care, a description
of the bug, along with various workarounds, can be found here:

  http://www.x86.org/errata/dec97/f00fbug.htm

Some discussion of which processors are really 100% compatible is here:

  http://linuxmafia.com/faq/Hardware/f00f-bug.html

Congratulations to AMD for not carrying compatibility too far here. :-)

What I hate about the workarounds is that they effectively preclude
kernel use of large page mappings, because (a) the fix relies on a
mapping trick, and (b) extending the mapping trick to a 4M boundary
makes an unholy mess.

TLB misses in a microkernel are important. Because of this, there is a
LOT of incentive to make use of large page mappings for the kernel. On
many processors, those entries will get broken back into 4K entries by
the I-TLB, so you still need to be careful about code organization, but
at least you can generate wins for D-TLB references.

The F00F bug screws this up horribly, because it effectively demands
that the exception vector table live in a 4K mapping.

This bug only impacts P5 processors, so it may be the right thing to
just ignore it entirely -- most of those machines are now dead. For the
moment, that is what I am going to do.

Why am I whining?

Until recently, I had been working fairly hard to rearrange the kernel
so that large page mappings could be effectively used. The F00F bug
introduces the sad consequence that I-mappings must remain small page
mappings. If we decide that P5 support is important, some of that
benefit is undone.

shap